The present invention relates generally to phase lock loop frequency synthesizers, and more specifically to a direct digital synthesizer driven phase lock loop frequency synthesizer which is particularly suitable for use in applications, such as digital cellular telephony, where communications channels are switched from one channel to another at significantly high speeds.
As shown in FIG. 1a, a typical conventional phase lock loop frequency synthesizer synthesizes a frequency by using a control voltage to drive a voltage controlled oscillator 5 which generates a signal of frequency f.sub.o near the desired frequency. A frequency divider 6 is used to divide the VCO signal output frequency by an integer value N to produce a signal of frequency f.sub.s. The frequency-f.sub.s signal is input along with a signal of reference frequency f.sub.r to a phase detector 3. The phase detector compares the frequencies of the two input signals and outputs a voltage proportional to the difference in frequency of the two input signals. The output of the phase detector 3 is coupled through a loop filter 4, where it is input to the VCO 5 as the control voltage. The reference frequency (f.sub.r) signal is derived by a divide-by-M frequency divider 2 which divides a signal of high accuracy frequency f.sub.x from a master oscillator 1 by a constant integer value M. The integer N of frequency divider 6 is variable by an incremental frequency control voltage so that if the VCO 5 were generating exactly the desired frequency, the resultant frequency-f.sub.s signal would be exactly the same frequency as reference frequency f.sub.r and the following relation holds: EQU f.sub.o =(N)(f.sub.x /M) (1)
As the frequency control voltage is varied, the output frequency f.sub.o varies accordingly from one frequency, or channel, to another, and the minimum channel separation, or frequency step size or resolution, .DELTA.f.sub.o is given by: EQU .DELTA.f.sub.o =f.sub.x /M (2)
To insure loop stability the loop filter needs to have a cutoff frequency much lower than the reference frequency. However, the lock-in time of the frequency synthesizer is inversely proportional to the cutoff frequency. Since the reference frequency is predetermined, the lock-in time cannot be reduced and hence, is a detrimental factor to achieve high speed channel switching.
This slow lock-in operation is overcome by techniques shown and described in U.S. Pat. No. 4,965,533. To provide mathematical analysis of this patent, two embodiments of the prior art PLL frequency synthesizer are shown respectively in FIGS. 1b and 1c of this specification. One of the prior-art embodiment, shown in FIG. 1b, incorporates a direct digital synthesizer (DDS) 7 that is clocked by the master oscillator to serve as the source of the reference frequency for the phase lock loop. The DDS typically comprises a phase accumulator which receives a digital fine frequency control signal .DELTA.X to determine the phase increment for accumulation at the master clock rate. The accumulated phase value is output to a sine lookup table, which stores sine values and provides an output signal, indicative of the digital representation of a periodic waveform, as an input to a digital-to-analog converter. The output of the D/A converter is filtered by a low-pass filter 8 and input to the frequency divider 2, whose output is used as a variable reference frequency input to the phase detector. Thus, frequency divider 6 operates as a constant-value divider. When the accumulated phase reaches a certain threshold, the phase accumulator automatically resets itself to repeat the accumulation process. Thus, the phase accumulator can be said to operate with a modulo value. If this modulo value is represented as L, the reference frequency f.sub.r is given by: EQU f.sub.r =(f.sub.x)(.DELTA.X)/L (3)
and the synthesizer output frequency f.sub.o is expressed by: EQU f.sub.o =(N)(f.sub.r)=(N)(f.sub.x)(.DELTA.X)/L (4)
Since the frequency control is provided by DDS 7 in response to increment .DELTA.X, the minimum frequency step size .DELTA.f.sub.o is equal to a variation in the output frequency f.sub.o that occurs in response to an increment of .DELTA.X=1. Therefore, the following relation holds: EQU .DELTA.f.sub.o =(N)(f.sub.x /L) (5)
From Equations (3) and (5), the relation f.sub.r =(.DELTA.f.sub.o)(.DELTA.X/N) is obtained. This implies that by setting the increment .DELTA.X at a value greater than the integer N, the reference frequency f.sub.r can be set higher than the reference frequency of the FIG. 1a frequency synthesizer for a given minimum frequency resolution. For example, using a minimum frequency step size of 25 kHz, a master clock frequency f.sub.x =12.8 MHz and an integer N=1024, Equation (5) gives a modulo value L=2.sup.19. If the output frequency f.sub.o is chosen at 1 GHz, Equation (4) gives an increment .DELTA.X=40000, a value much greater than the integer N=1024. Thus, a reference frequency of 976.5625 kHz, much higher than .DELTA.f.sub.o =25 kHz, is obtained. While high speed convergence of the phase lock loop can be achieved, variation of the reference frequency causes a control voltage variation at the input of the VCO, a variation known as "reference leak", which would result in the transmission of spurious frequencies. A band rejection filter must be provided as part of the loop filter 4 to eliminate the undesired spurious transmission. However, it is difficult to eliminate the undesirable components uniformly across all channels of the frequency synthesizer.
According to the other prior art technique shown in FIG. 1c, DDS 7 and low-pass filter 8 are provided in the phase lock loop, following the output of divider 6, so that the divided frequency signal f.sub.s is caused to vary in response to phase increment .DELTA.X, while reference frequency f.sub.r remains constant, thus giving the following relations: EQU f.sub.s =(f.sub.o)(.DELTA.X)/(N)(L) (6) EQU f.sub.x /M=(f.sub.o)(.DELTA.X)/(N)(L) (7) EQU Thus, f.sub.o =(f.sub.x)(N)(L)/(M)(.DELTA.X) (8)
While this technique eliminates the reference leak problem, the fact that the output frequency f.sub.o varies inversely proportional to the increment .DELTA.X, as given by Equation (8), makes it impossible to set all channels of the synthesizer at precisely equal frequency intervals.